UVD_MPC_SET_MUXA1__VARA_7__SHIFT  511 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c
UVD_MPC_SET_MUXA1__VARA_7__SHIFT  496 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT  528 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT  530 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT  611 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT 1118 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT 2624 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA1__VARA_7__SHIFT 2859 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc