UVD_MPC_SET_MUXA1__VARA_5__SHIFT  507 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x00000000
UVD_MPC_SET_MUXA1__VARA_5__SHIFT  492 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT  524 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT  526 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT  609 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT 1116 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT 2622 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
UVD_MPC_SET_MUXA1__VARA_5__SHIFT 2857 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0