UVD_MPC_SET_MUXA0__VARA_4__SHIFT  505 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018
UVD_MPC_SET_MUXA0__VARA_4__SHIFT  490 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT  522 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT  524 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT  602 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT 1109 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT 2615 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
UVD_MPC_SET_MUXA0__VARA_4__SHIFT 2850 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18