UVD_MPC_SET_MUXA0__VARA_3__SHIFT  503 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x00000012
UVD_MPC_SET_MUXA0__VARA_3__SHIFT  488 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT  520 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT  522 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT  601 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT 1108 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT 2614 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
UVD_MPC_SET_MUXA0__VARA_3__SHIFT 2849 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12