UVD_MPC_SET_MUXA0__VARA_2__SHIFT  501 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c
UVD_MPC_SET_MUXA0__VARA_2__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT  518 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT  520 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT  600 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT 1107 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT 2613 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
UVD_MPC_SET_MUXA0__VARA_2__SHIFT 2848 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc