UVD_MPC_SET_MUXA0__VARA_2_MASK 500 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003f000L UVD_MPC_SET_MUXA0__VARA_2_MASK 485 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 UVD_MPC_SET_MUXA0__VARA_2_MASK 517 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 UVD_MPC_SET_MUXA0__VARA_2_MASK 519 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 UVD_MPC_SET_MUXA0__VARA_2_MASK 605 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L UVD_MPC_SET_MUXA0__VARA_2_MASK 1112 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L UVD_MPC_SET_MUXA0__VARA_2_MASK 2618 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L UVD_MPC_SET_MUXA0__VARA_2_MASK 2853 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L