UVD_MPC_SET_MUXA0__VARA_1__SHIFT 499 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 484 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 516 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 518 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 599 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 1106 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 2612 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 UVD_MPC_SET_MUXA0__VARA_1__SHIFT 2847 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6