UVD_MPC_SET_MUXA0__VARA_0__SHIFT 497 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 482 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 514 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 516 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 598 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 1105 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 2611 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 UVD_MPC_SET_MUXA0__VARA_0__SHIFT 2846 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0