UVD_MPC_SET_MUXA0__VARA_0_MASK 496 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003fL UVD_MPC_SET_MUXA0__VARA_0_MASK 481 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f UVD_MPC_SET_MUXA0__VARA_0_MASK 513 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f UVD_MPC_SET_MUXA0__VARA_0_MASK 515 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f UVD_MPC_SET_MUXA0__VARA_0_MASK 603 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL UVD_MPC_SET_MUXA0__VARA_0_MASK 1110 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL UVD_MPC_SET_MUXA0__VARA_0_MASK 2616 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL UVD_MPC_SET_MUXA0__VARA_0_MASK 2851 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL