UVD_MPC_CNTL__PERF_RST_MASK  486 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L
UVD_MPC_CNTL__PERF_RST_MASK  473 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK 0x40
UVD_MPC_CNTL__PERF_RST_MASK  505 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK 0x40
UVD_MPC_CNTL__PERF_RST_MASK  507 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK 0x40
UVD_MPC_CNTL__PERF_RST_MASK 2602 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK                                                                           0x00000040L
UVD_MPC_CNTL__PERF_RST_MASK 2837 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_MPC_CNTL__PERF_RST_MASK                                                                           0x00000040L