UVD_MPC_CNTL__DBG_MUX_MASK  484 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000700L
UVD_MPC_CNTL__DBG_MUX_MASK  475 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_MPC_CNTL__DBG_MUX_MASK 0x700
UVD_MPC_CNTL__DBG_MUX_MASK  507 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
UVD_MPC_CNTL__DBG_MUX_MASK  509 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00