UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 1023 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 1011 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000