UVD_LMI_STATUS__WRITE_CLEAN__SHIFT  385 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x00000001
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT  384 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT  416 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT  418 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 1057 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT                                                                    0x1
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 2430 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT                                                                    0x1
UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 3381 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT                                                                    0x1