UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT  384 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x00000002
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT  386 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT  418 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT  420 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 1058 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT                                                                0x2
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 2431 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT                                                                0x2
UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 3382 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT                                                                0x2