UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT  381 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x00000003
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT  388 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT  420 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT  422 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 1059 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT                                                           0x3
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 2432 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT                                                           0x3
UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 3383 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT                                                           0x3