UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT  379 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x00000005
UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT  392 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT  424 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT  426 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 2434 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT                                                                0x5
UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 3385 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT                                                                0x5