UVD_LMI_STATUS__READ_CLEAN__SHIFT  367 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x00000000
UVD_LMI_STATUS__READ_CLEAN__SHIFT  382 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
UVD_LMI_STATUS__READ_CLEAN__SHIFT  414 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
UVD_LMI_STATUS__READ_CLEAN__SHIFT  416 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
UVD_LMI_STATUS__READ_CLEAN__SHIFT 1056 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT                                                                     0x0
UVD_LMI_STATUS__READ_CLEAN__SHIFT 2429 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT                                                                     0x0
UVD_LMI_STATUS__READ_CLEAN__SHIFT 3380 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_STATUS__READ_CLEAN__SHIFT                                                                     0x0