UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT  351 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT  350 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT  382 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT  384 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT  505 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 1027 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 2396 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 3347 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0