UVD_LMI_CTRL__CRC_SEL__SHIFT  325 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0x0000000f
UVD_LMI_CTRL__CRC_SEL__SHIFT  364 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT  396 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT  398 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT  512 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT 1034 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT 2403 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
UVD_LMI_CTRL__CRC_SEL__SHIFT 3354 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf