UVD_LMI_CTRL__CRC_RESET__SHIFT  323 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0x0000000e
UVD_LMI_CTRL__CRC_RESET__SHIFT  362 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT  394 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT  396 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT  511 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT 1033 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT 2402 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
UVD_LMI_CTRL__CRC_RESET__SHIFT 3353 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe