UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  297 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x00000007
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  308 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  340 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  342 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  472 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT  989 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 2054 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 3292 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7