UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 728 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 703 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 706 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4