UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 824 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 827 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L