UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT  257 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x00000000
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT   50 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT   50 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT   50 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT  123 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT  313 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 3173 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 2202 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0