UVD_GPCOM_VCPU_CMD__CMD__SHIFT  251 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x00000001
UVD_GPCOM_VCPU_CMD__CMD__SHIFT   44 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT   44 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT   44 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT  114 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT  304 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT 3164 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
UVD_GPCOM_VCPU_CMD__CMD__SHIFT 2193 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1