UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT  250 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x00000000
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT   42 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT   42 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT   42 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT  113 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT  303 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 3163 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 2192 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0