UVD_CGC_UDEC_STATUS__MP_VCLK_MASK  230 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L
UVD_CGC_UDEC_STATUS__MP_VCLK_MASK  295 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
UVD_CGC_UDEC_STATUS__MP_VCLK_MASK  319 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
UVD_CGC_UDEC_STATUS__MP_VCLK_MASK  321 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 2007 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK                                                                     0x00004000L
UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 2055 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK                                                                     0x00004000L