UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT  221 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x00000007
UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT  282 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT  306 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT  308 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 1985 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT                                                                   0x7
UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 2033 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT                                                                   0x7