UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 220 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 281 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 305 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 307 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 2000 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 2048 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L