UVD_CGC_UDEC_STATUS__CM_DCLK_MASK  208 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L
UVD_CGC_UDEC_STATUS__CM_DCLK_MASK  275 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
UVD_CGC_UDEC_STATUS__CM_DCLK_MASK  299 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
UVD_CGC_UDEC_STATUS__CM_DCLK_MASK  301 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 1997 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK                                                                     0x00000010L
UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 2045 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK                                                                     0x00000010L