UVD_CGC_STATUS__WCB_SCLK_MASK  206 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
UVD_CGC_STATUS__WCB_SCLK_MASK  211 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
UVD_CGC_STATUS__WCB_SCLK_MASK  227 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
UVD_CGC_STATUS__WCB_SCLK_MASK  229 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
UVD_CGC_STATUS__WCB_SCLK_MASK  902 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L
UVD_CGC_STATUS__WCB_SCLK_MASK 1921 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L
UVD_CGC_STATUS__WCB_SCLK_MASK 1971 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L