UVD_CGC_STATUS__VCPU_VCLK__SHIFT  205 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x0000001a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT  216 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT  232 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT  234 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT  872 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT 1892 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a
UVD_CGC_STATUS__VCPU_VCLK__SHIFT 1942 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a