UVD_CGC_STATUS__UDEC_VCLK__SHIFT 201 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x00000005 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 174 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 190 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 192 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 851 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 1871 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 UVD_CGC_STATUS__UDEC_VCLK__SHIFT 1921 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5