UVD_CGC_STATUS__UDEC_DCLK_MASK  196 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
UVD_CGC_STATUS__UDEC_DCLK_MASK  171 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
UVD_CGC_STATUS__UDEC_DCLK_MASK  187 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
UVD_CGC_STATUS__UDEC_DCLK_MASK  189 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
UVD_CGC_STATUS__UDEC_DCLK_MASK  882 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L
UVD_CGC_STATUS__UDEC_DCLK_MASK 1901 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L
UVD_CGC_STATUS__UDEC_DCLK_MASK 1951 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L