UVD_CGC_STATUS__SYS_SCLK_MASK  192 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
UVD_CGC_STATUS__SYS_SCLK_MASK  163 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
UVD_CGC_STATUS__SYS_SCLK_MASK  179 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
UVD_CGC_STATUS__SYS_SCLK_MASK  181 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
UVD_CGC_STATUS__SYS_SCLK_MASK  878 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L
UVD_CGC_STATUS__SYS_SCLK_MASK 1897 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L
UVD_CGC_STATUS__SYS_SCLK_MASK 1947 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L