UVD_CGC_STATUS__SYS_DCLK_MASK  190 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
UVD_CGC_STATUS__SYS_DCLK_MASK  165 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
UVD_CGC_STATUS__SYS_DCLK_MASK  181 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
UVD_CGC_STATUS__SYS_DCLK_MASK  183 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
UVD_CGC_STATUS__SYS_DCLK_MASK  879 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L
UVD_CGC_STATUS__SYS_DCLK_MASK 1898 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L
UVD_CGC_STATUS__SYS_DCLK_MASK 1948 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L