UVD_CGC_STATUS__REGS_VCLK_MASK  184 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
UVD_CGC_STATUS__REGS_VCLK_MASK  183 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
UVD_CGC_STATUS__REGS_VCLK_MASK  199 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
UVD_CGC_STATUS__REGS_VCLK_MASK  201 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
UVD_CGC_STATUS__REGS_VCLK_MASK  888 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L
UVD_CGC_STATUS__REGS_VCLK_MASK 1907 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L
UVD_CGC_STATUS__REGS_VCLK_MASK 1957 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L