UVD_CGC_STATUS__REGS_SCLK_MASK  182 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
UVD_CGC_STATUS__REGS_SCLK_MASK  181 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
UVD_CGC_STATUS__REGS_SCLK_MASK  197 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
UVD_CGC_STATUS__REGS_SCLK_MASK  199 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
UVD_CGC_STATUS__REGS_SCLK_MASK  887 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L
UVD_CGC_STATUS__REGS_SCLK_MASK 1906 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L
UVD_CGC_STATUS__REGS_SCLK_MASK 1956 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L