UVD_CGC_STATUS__RBC_SCLK_MASK  180 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
UVD_CGC_STATUS__RBC_SCLK_MASK  185 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
UVD_CGC_STATUS__RBC_SCLK_MASK  201 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
UVD_CGC_STATUS__RBC_SCLK_MASK  203 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
UVD_CGC_STATUS__RBC_SCLK_MASK  889 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L
UVD_CGC_STATUS__RBC_SCLK_MASK 1908 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L
UVD_CGC_STATUS__RBC_SCLK_MASK 1958 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L