UVD_CGC_STATUS__MPRD_VCLK__SHIFT  179 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x00000012
UVD_CGC_STATUS__MPRD_VCLK__SHIFT  200 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
UVD_CGC_STATUS__MPRD_VCLK__SHIFT  216 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
UVD_CGC_STATUS__MPRD_VCLK__SHIFT  218 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
UVD_CGC_STATUS__MPRD_VCLK__SHIFT  864 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12
UVD_CGC_STATUS__MPRD_VCLK__SHIFT 1884 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12
UVD_CGC_STATUS__MPRD_VCLK__SHIFT 1934 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12