UVD_CGC_STATUS__MPRD_VCLK_MASK  178 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
UVD_CGC_STATUS__MPRD_VCLK_MASK  199 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
UVD_CGC_STATUS__MPRD_VCLK_MASK  215 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
UVD_CGC_STATUS__MPRD_VCLK_MASK  217 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
UVD_CGC_STATUS__MPRD_VCLK_MASK  896 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L
UVD_CGC_STATUS__MPRD_VCLK_MASK 1915 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L
UVD_CGC_STATUS__MPRD_VCLK_MASK 1965 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L