UVD_CGC_STATUS__MPRD_SCLK__SHIFT  177 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x00000010
UVD_CGC_STATUS__MPRD_SCLK__SHIFT  196 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
UVD_CGC_STATUS__MPRD_SCLK__SHIFT  212 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
UVD_CGC_STATUS__MPRD_SCLK__SHIFT  214 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
UVD_CGC_STATUS__MPRD_SCLK__SHIFT  862 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10
UVD_CGC_STATUS__MPRD_SCLK__SHIFT 1882 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10
UVD_CGC_STATUS__MPRD_SCLK__SHIFT 1932 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10