UVD_CGC_STATUS__MPRD_DCLK__SHIFT  175 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x00000011
UVD_CGC_STATUS__MPRD_DCLK__SHIFT  198 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
UVD_CGC_STATUS__MPRD_DCLK__SHIFT  214 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
UVD_CGC_STATUS__MPRD_DCLK__SHIFT  216 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
UVD_CGC_STATUS__MPRD_DCLK__SHIFT  863 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11
UVD_CGC_STATUS__MPRD_DCLK__SHIFT 1883 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11
UVD_CGC_STATUS__MPRD_DCLK__SHIFT 1933 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11