UVD_CGC_STATUS__MPRD_DCLK_MASK  174 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
UVD_CGC_STATUS__MPRD_DCLK_MASK  197 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
UVD_CGC_STATUS__MPRD_DCLK_MASK  213 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
UVD_CGC_STATUS__MPRD_DCLK_MASK  215 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
UVD_CGC_STATUS__MPRD_DCLK_MASK  895 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L
UVD_CGC_STATUS__MPRD_DCLK_MASK 1914 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L
UVD_CGC_STATUS__MPRD_DCLK_MASK 1964 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L