UVD_CGC_STATUS__MPEG2_VCLK__SHIFT  173 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x00000008
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT  180 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT  196 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT  198 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT  854 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 1874 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8
UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 1924 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8