UVD_CGC_STATUS__MPEG2_SCLK__SHIFT  171 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x00000006
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT  176 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT  192 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT  194 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT  852 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 1872 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6
UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 1922 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6