UVD_CGC_STATUS__MPEG2_SCLK_MASK  170 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
UVD_CGC_STATUS__MPEG2_SCLK_MASK  175 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
UVD_CGC_STATUS__MPEG2_SCLK_MASK  191 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
UVD_CGC_STATUS__MPEG2_SCLK_MASK  193 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
UVD_CGC_STATUS__MPEG2_SCLK_MASK  884 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L
UVD_CGC_STATUS__MPEG2_SCLK_MASK 1903 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L
UVD_CGC_STATUS__MPEG2_SCLK_MASK 1953 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L