UVD_CGC_STATUS__MPEG2_DCLK__SHIFT  169 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x00000007
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT  178 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT  194 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT  196 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT  853 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 1873 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7
UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 1923 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7