UVD_CGC_STATUS__MPC_SCLK__SHIFT  167 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013
UVD_CGC_STATUS__MPC_SCLK__SHIFT  202 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
UVD_CGC_STATUS__MPC_SCLK__SHIFT  218 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
UVD_CGC_STATUS__MPC_SCLK__SHIFT  220 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
UVD_CGC_STATUS__MPC_SCLK__SHIFT  865 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13
UVD_CGC_STATUS__MPC_SCLK__SHIFT 1885 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13
UVD_CGC_STATUS__MPC_SCLK__SHIFT 1935 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13