UVD_CGC_STATUS__MPC_SCLK_MASK  166 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
UVD_CGC_STATUS__MPC_SCLK_MASK  201 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
UVD_CGC_STATUS__MPC_SCLK_MASK  217 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
UVD_CGC_STATUS__MPC_SCLK_MASK  219 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
UVD_CGC_STATUS__MPC_SCLK_MASK  897 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L
UVD_CGC_STATUS__MPC_SCLK_MASK 1916 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L
UVD_CGC_STATUS__MPC_SCLK_MASK 1966 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L